View M58LR128GU_7750556.PDF datasheet online --- IC-ON-LINE

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june 2006 rev 1 1/114 1 m58lr256gu, m58lr256gl M58LR128GU, m58lr128gl 128 and 256mbit (x16, mux i/o, mult iple bank, multi-level, burst) 1.8v supply flash memories feature summary supply voltage ?v dd = 1.7v to 2.0v for program, erase and read ?v ddq = 1.7v to 2.0v for i/o buffers ?v pp = 9v for fast program multiplexed address/data synchronous / asynchronous read ? synchronous burst read mode: 66mhz ? random access: 85ns (M58LR128GU/l) 90ns (m58lr256gu/l) synchronous burst read suspend programming time ? 10s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 16 mbit (m58lr256gu/l) or 8 mbit (M58LR128GU/l) banks ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp for block lock-down ? absolute write protection with v pp = v ss security ? 64 bit unique device number ? 2112 bit user programmable otp cells common flash interface (cfi) 100,000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? top device codes: m58lr256gu: 882ch M58LR128GU: 882eh ? bottom device codes m58lr256gl: 882dh m58lr128gl: 882fh ecopack? packages available vfbga44 (zc) 8 x 10mm vfbga44 (zb) 7.7 x 9mm fbga www.st.com
contents m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 2/114 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 address inputs (adq0-adq15 and a16-amax) . . . . . . . . . . . . . . . . . . . 15 2.2 data input/output (adq0-adq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.12 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.13 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.14 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.15 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl contents 3/114 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 buffer program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.9 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . 26 4.9.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.9.2 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.9.3 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.11 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.12 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.13 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.14 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.15 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.16 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.8 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . 38 6 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 x-latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.4 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.6 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.7 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
contents m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 4/114 6.8 wrap burst bit (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.9 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.1 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 50 9 block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 reading a block?s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.4 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.5 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 53 10 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 55 11 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 appendix b common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 appendix c flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 appendix d command interface state ta bles. . . . . . . . . . . . . . . . . . . . . . . . . . . 105 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl list of tables 5/114 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. m58lr256gu/l bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. M58LR128GU/l bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. protection register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. x-latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 12. configuration register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 14. wait at the boundary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 15. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 16. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 17. dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 18. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 20. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 21. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 22. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 23. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 24. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 25. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 26. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 27. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 28. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 29. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 30. vfbga44 8 10mm - 10 4 ball array, 0.50mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 31. vfbga44 7.7 9mm - 10 4 ball array, 0.50mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 32. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 33. m58lr256gu - parameter bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 34. m58lr256gu - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 35. m58lr256gu - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 36. m58lr256gl - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 37. m58lr256gl - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 38. m58lr256gl - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 39. M58LR128GU - parameter bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 40. M58LR128GU - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 41. M58LR128GU - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 42. m58lr128gl - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 43. m58lr128gl - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 44. m58lr128gl - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 45. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 46. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
list of tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 6/114 table 47. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 table 48. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 49. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 50. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 51. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 52. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 53. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 54. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 55. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 56. command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 107 table 57. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 58. command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 111 table 59. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl list of figures 7/114 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. vfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. m58lr256gu/l memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. M58LR128GU/l memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6. x-latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 figure 9. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 10. asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 11. synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 12. single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 13. synchronous burst read suspend ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 14. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 15. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 16. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 17. reset and power-up ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 18. vfbga44 8 10mm - 10 4 ball array, 0.50mm pitch, bottom view package outline. . . . 72 figure 19. vfbga44 7.7 9mm - 10 4 ball array, 0.50mm pitch, bottom view package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 20. vfbga44 daisy chain - package connections (top view through package) . . . . . . . . . . . . 76 figure 21. vfbga44 daisy chain - pcb connection propos al (top view through package). . . . . . . . . 77 figure 22. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 figure 23. buffer program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 24. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 25. block erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 26. erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 27. locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 28. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . 103 figure 29. buffer enhanced factory program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . 104
summary description m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 8/114 1 summary description the M58LR128GU/l and m58lr256gu/l are 128 mbit (8 mbit x16) and 256 mbit (16 mbit x16) non-volatile flash memories, respective ly. they will be referred to as m58lrxxxgu/l in the rest of the document unless otherwise specified. the m58lrxxxgu/l may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7v to 2.0v v dd supply for the circuitry and a 1.7v to 2.0v v ddq supply for the input/output pins. an optional 9v v pp power supply is provided to speed up factory programming. the first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus adq0-adq15. the remaining address lines a16-a23 (m58lr256gu/l) or a16-a22 (M58LR128GU/l) are the most significant bit addresses. the devices feature an asymmetrical block architecture and are based on a multi-level cell technology. m58lr256gu/l has an array of 259 blocks, and is divided into 16 mbit banks. there are 15 banks each containing 16 main blocks of 64 kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 15 main blocks of 64 kwords. M58LR128GU/l has an array of 131 blocks, and is divided into 8 mbit banks. there are 15 banks each containing 8 main blocks of 64 kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 7 main blocks of 64 kwords. the multiple bank architecture allows dual operations, while programming or erasing in one bank, read operations are possible in other ba nks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in tables 2 and 3 , and the memory maps are shown in figures 3 and 4 . the parameter blocks are located at the top of the memory address space for the m58lr256gu and M58LR128GU, and at the bottom for the m58lr256gl and m58lr128gl. each block can be erased separately. erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. program can be suspended to read data at any memory location except for the one being programmed, and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . there is a buffer enhanced factory programming command available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66mhz. the synchronous burst read operation can be suspended and resumed. the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device autom atically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl summary description 9/114 the m58lrxxxgu/l features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power- up. the device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 one-time-programmable (otp) protection registers of 128 bits each. the first protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 64 bit segment one- time-programmable (otp) by the user. the user programmable segment can be permanently protected. figure 5 , shows the protection register memory map. the m58lr256gu/l is offered in a vfbga44, 8 x 10mm, 0.50mm pitch package whereas the M58LR128GU/l is offered in a vfbga44, 7.7 x 9mm, 0.50mm pitch package. the memories are supplied with all the bits erased (set to ?1?). figure 1. logic diagram 1. amax is equal to a22 for the M58LR128GU/l and to a23 for the m58lr256gu/l. ai10088 a16-amax (1) w adq0- adq15 v dd m58lr256gu m58lr256gl M58LR128GU m58lr128gl e v ss 16 g rp wp v ddq v pp l k wait v ssq
summary description m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 10/114 table 1. signal names a16-amax (1) 1. amax is equal to a22 for the M58LR128GU/l and to a23 for the m58lr256gu/l. address inputs adq0-adq15 data input/outputs or address inputs, command inputs e chip enable g output enable w write enable rp reset wp write protect kclock l latch enable wait wait v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally du do not use
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl summary description 11/114 figure 2. vfbga connections (top view through package) 1. ball d7 is a23 in the m58lr256gu/l. it is no t connected internally (nc) in the M58LR128GU/l. ai10089 v ddq adq10 adq11 adq4 adq5 v ssq adq14 adq15 adq9 adq2 adq3 adq6 adq7 v ss a18 wp rp a23 (1) l a20 a16 v ddq a19 v pp w v dd k wait 6 5 4 3 2 1 adq1 adq8 e a17 adq0 g 8 7 adq13 adq12 v ss v ssq nc nc 10 9 nc nc a21 a22 14 13 12 11 h g f e d c b a
summary description m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 12/114 table 2. m58lr256gu/l bank architecture number bank size parameter blocks main blocks parameter bank 16 mbits 4 blocks of 16 kwords 15 blocks of 64 kwords bank 1 16 mbits - 16 blocks of 64 kwords bank 2 16 mbits - 16 blocks of 64 kwords bank 3 16 mbits - 16 blocks of 64 kwords ---- ---- ---- ---- bank 14 16 mbits - 16 blocks of 64 kwords bank 15 16 mbits - 16 blocks of 64 kwords table 3. M58LR128GU/l bank architecture number bank size parameter blocks main blocks parameter bank 8 mbits 4 blocks of 16 kwords 7 blocks of 64 kwords bank 1 8 mbits - 8 blocks of 64 kwords bank 2 8 mbits - 8 blocks of 64 kwords bank 3 8 mbits - 8 blocks of 64 kwords ---- ---- ---- ---- bank 14 8 mbits - 8 blocks of 64 kwords bank 15 8 mbits - 8 blocks of 64 kwords
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl summary description 13/114 figure 3. m58lr256gu/l memory map ai09317 m58lr256gu - top boot block address lines a23-a16 and adq15-adq0 16 main blocks bank 15 m58lr256gl - bottom boot block address lines a23-a16 and adq15-adq0 64 kword 000000h 00ffffh 64 kword 0f0000h 0fffffh 64 kword c00000h c0ffffh 64 kword cf0000h cfffffh 64 kword d00000h d0ffffh 64 kword df0000h dfffffh 64 kword e00000h e0ffffh 64 kword ef0000h efffffh 64 kword f00000h f0ffffh 64 kword fe0000h feffffh 16 kword ff0000h ff3fffh 16 kword ffc000h ffffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 1f0000h 1fffffh 64 kword 200000h 20ffffh 64 kword 2f0000h 2fffffh 64 kword 300000h 30ffffh 64 kword 3f0000h 3fffffh 64 kword f00000h f0ffffh 64 kword ff0000h ffffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 16 main blocks 16 main blocks 16 main blocks 15 main blocks 4 parameter blocks 15 main blocks 16 main blocks 16 main blocks 16 main blocks 16 main blocks
summary description m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 14/114 figure 4. M58LR128GU/l memory map ai09861 M58LR128GU - top boot block address lines a22-a16 and adq15-adq0 8 main blocks bank 15 m58lr128gl - bottom boot block address lines a22-a16 and adq15-adq0 64 kword 000000h 00ffffh 64 kword 070000h 07ffffh 64 kword 600000h 60ffffh 64 kword 670000h 67ffffh 64 kword 680000h 68ffffh 64 kword 6f0000h 6fffffh 64 kword 700000h 70ffffh 64 kword 770000h 77ffffh 64 kword 780000h 78ffffh 64 kword 7e0000h 7effffh 16 kword 7f0000h 7f3fffh 16 kword 7fc000h 7fffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 070000h 07ffffh 64 kword 080000h 08ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 170000h 17ffffh 64 kword 180000h 18ffffh 64 kword 1f0000h 1fffffh 64 kword 780000h 78ffffh 64 kword 7f0000h 7fffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 4 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl signal descriptions 15/114 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (adq 0-adq15 and a16-amax) amax is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data input/output (adq0-adq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. 2.4 output enable (g ) the output enable input controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable input controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. 2.6 write protect (wp ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to table 18: lock status ).
signal descriptions m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 16/114 2.7 reset (rp ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 23: dc characteristics - currents , for the value of i dd2. after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to table 24: dc characteristics - voltages ). 2.8 latch enable (l ) latch enable latches the adq0-adq15 and a16-amax address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . 2.9 clock (k) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is ignored during asynchronous read and in write operations. 2.10 wait (wait) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih or reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. the wait signal is forced deasserted when output enable is at v ih . 2.11 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). 2.12 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl signal descriptions 17/114 2.13 v pp program supply voltage v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk gives absolute protection against program or erase, while v pp in the v pp1 range enables these functions (see tables 23 and 24 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed. 2.14 v ss ground v ss ground is the reference for the core supply. it must be connected to the system ground. 2.15 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inhere ntly low inductance capacitors should be as close as possible to the package). see figure 9: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
bus operations m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 18/114 3 bus operations there are six standard bus operations that control the device. these are bus read, bus write, address latch, output disable, standby and reset. see table 4: bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. 3.1 bus read bus read operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figures 10 , 11 and 12 read ac waveforms, and tables 25 and 26 read ac characteristics, for details of when the output becomes valid. 3.2 bus write bus write operations write commands to the memory or latch input data to be programmed. a bus write operatio n is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses must be latched prior to the write operation by toggling latch enable. in this case the latch enable must be tied to v ih during the bus write operation. see figures 15 and 16 , write ac waveforms, and tables 27 and 28 , write ac characteristics, for details of the timing requirements. 3.3 address latch address latch operations input valid addresses. both chip enable and latch enable must be at v il during address latch operations. the addresses are latched on the rising edge of latch enable. 3.4 output disable the outputs are high impedance when the output enable is at v ih .
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl bus operations 19/114 3.5 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in standby when chip enable and reset are at v ih . the power consumption is reduced to the standby level i dd3 and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. 3.6 reset during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the reset level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 4. bus operations (1) 1. x = don't care. operation e g w l rp wait (2) 2. wait signal polarity is configured us ing the set configuration register command. adq15-adq0 bus read v il v il v ih v ih v ih data output bus write v il v ih v il v ih v ih data input address latch v il v ih xv il v ih address input output disable v il v ih v ih v ih v ih hi-z standby v ih xxxv ih hi-z hi-z reset x x x x v il hi-z hi-z
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 20/114 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller handles all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequences must be followed exactly. any invalid combination of commands will be ignored. refer to table 5: command codes , table 6: standard commands , table 7: factory program command , and appendix d: command interface state tables , for a summary of the command interface. table 5. command codes hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 40h program setup 50h clear status register 60h block lock setup, block unlock setup, block lock down setup and set configuration register setup 70h read status register 80h buffer enhanced factory program 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block erase confirm, block unlock confirm or buffer program confirm e8h buffer program ffh read array
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 21/114 4.1 read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the r ead array command. once a bank is in read array mode, subsequent read operations will output the data from the memory array. a read array command can be issued to any banks while programming or erasing in another bank. if the read array command is issued to a bank currently executing a program or erase operation, the ba nk will return to read array mode bu t the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. the read modes of other banks are not affected. 4.2 read status register command the device contains a status register that is used to monitor program or erase operations. the read status register command is used to read the contents of the status register for the addressed bank. one bus write cycle is required to issue the read status register command. once a bank is in read status register mo de, subsequent read oper ations will output th e contents of the status register. the status register data is la tched on the falling edge of the ch ip enable or output enable signals. either chip enable or output enable must be toggled to update the status register data the read status register command can be issued at any time, even during program or erase operations. the read stat us register command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations sh ould be used to read the status register. a read array command is required to return the bank to read array mode. see ta bl e 1 0 for the description of the status register bits.
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 22/114 4.3 read electronic signature command the read electronic signature command is used to read the manufacturer and device codes, the lock status of the addressed bank, the protection register, and the configuration register. one bus write cycle is required to issue the read electronic signature command. once a bank is in read electronic signature mode, subsequent read operations in the same bank will output the manufacturer code, the device co de, the lock status of the addressed bank, the protection register, or the configuration register (see ta bl e 8 ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register program operations. dual operations between the parameter bank and the electronic signature location are not allowed (see table 17: dual operation limitations for details). if a read electronic signature command is issu ed to a bank that is executing a program or erase operation the bank will go into read electronic si gnature mode. subsequent bus read cycles will output the electronic sig nature data and the prog ram/erase controller will continue to program or erase in the background. the read electronic signatur e command will only change the r ead mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the electronic signature. a read array command is required to return the bank to read array mode. 4.4 read cfi query command the read cfi query command is used to read data from the common flash interface (cfi). one bus write cycle is required to issue the read cfi query command. once a bank is in read cfi query mode, subsequent bus read operations in the same bank read from the common flash interface. the read cfi query command can be issued at any time, even during program or erase operations. if a read cfi query command is issued to a bank that is executing a program or erase operation the bank will go into read cfi query mode. subsequent bus read cycles will output the cfi data and the program/erase co ntroller will continue to program or erase in the background. the read cfi query command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read from the cfi. a read array command is required to return the bank to read array mode. dual operations between the parameter bank and the cfi memory space are not allowed (see table 17: dual operation limitations for details). see appendix b: common flash interface , tables 45 , 46 , 47 , 48 , 49 , 51 , 52 , 53 and 54 for details on the information contained in the common flash interface memory area.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 23/114 4.5 clear status register command the clear status register command can be used to reset (set to ?0?) all error bits (sr1, 3, 4 and 5) in the status register. one bus write cycle is required to issue the clear status register command. the clear status register command does not affect the read mode of the bank. the error bits in the status register do not automatically return to ?0? when a new command is issued. the error bits in the status register should be cleared before attempting a new program or erase command. 4.6 block erase command the block erase command is used to erase a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase oper ation will abort, the data in the block will not be changed and the st atus register will output the error. two bus write cycles are required to issue the command. the first bus cycle sets up the block erase command. the second latches the block address and starts the program/erase controller. if the second bus cycle is not the block erase confirm code, status register bits sr4 and sr5 are set and the command is aborted. once the command is issued the bank enters read status register mode and any read operation within the addre ssed bank will output the contents of the status re gister. a read array command is required to return the bank to read array mode. during block erase operations the bank containi ng the block being erased will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command, all other comm ands will be ignored. the block erase operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 19: program/erase times and endurance cycles . see appendix c , figure 25: block erase flowchart and pseudo code , for a suggested flowchart for using the block erase command.
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 24/114 4.7 program command the program command is used to program a single word to the memory array. if the block being programmed is protected, th en the program operation will abort, the data in the block will not be changed and the st atus register will output the error. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and data to be programmed and starts the program/erase controller. once the programming has started, read operations in the bank being programmed output the status register content. during a program operation, the bank cont aining the word being programmed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspe nd command, all other comman ds will be ignor ed. a read array command is required to return the bank to read array mode. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 19: program/erase times and endurance cycles . the program operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block must be erased before retrying the programming operation. see appendix c , figure 22: program flowchart and pseudo code , for the flowchart for using the program command.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 25/114 4.8 buffer program command the buffer program command makes use of the device?s 32-word write buffer to speed up programming. up to 32 words can be loaded into the write buffer. the buffer program command dramatically reduces in-system programming time compared to the standard non- buffered program command. four successive steps are required to issue the buffer program command. 1. the first bus write cycle sets up the buffer program command. the setup code can be addressed to any location within the targeted block. after the first bus write cycle, read operation s in the bank will output the contents of the status register. status register bit sr7 should be read to check that the buffer is available (sr7 = 1). if the buffer is not available (sr7 = 0), re-issue the buffer program command to update the status register contents. 2. the second bus write cycle sets up the nu mber of words to be programmed. value n is written to the same block address, where n+1 is the number of words to be programmed. 3. use n+1 bus write cycles to load the address and data for each word into the write buffer. addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. optimum performance is obtained when the start address corresponds to a 32 word boundary. if the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. the final bus write cycle confirms the buffer program command and starts the program operation. all the addresses used in the buffer program operation must lie within the same block. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abo rt the operation without affecting the data in the memory array. if the status register bits sr4 and sr5 are set to '1', the buffer program command is not accepted. clear the status register before re-issuing the command. if the block being programmed is protected an er ror will be set in the status register and the operation will abort without affectin g the data in the memory array. during buffer program operations the bank being programmed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command, all other comm ands will be ignored. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being programmed. see appendix c , figure 23: buffer program flowchart and pseudo code , for a suggested flowchart on using the buffer program command.
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 26/114 4.9 buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. it is used to program one or more write buffer(s) of 32 words to a block. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. only one block can be programmed at a time. if the block being programmed is protected, th en the program operation will abort, the data in the block will not be changed and the st atus register will output the error. the use of the buffer enhanced factory program command requires certain operating conditions: v pp must be set to v pph v dd must be within operating range ambient temperature t a must be 30c 10c the targeted block must be unlocked the start address must be aligned with the start of a 32 word buffer boundary the address must remain the start address throughout programming. dual operations are not supported during the buffer enhanced factory program operation and the command cannot be suspended. the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase, please refer to ta bl e 7 : fa c t o r y program command for detail information. 4.9.1 setup phase the buffer enhanced factory program command requires two bus write cycles to initiate the command. the first bus write cycle sets up the buffer enhanced factory program command. the second bus write cycle confirms the command. after the confirm command is issued, read operations output the contents of the status register. the read status regi ster command must not be issu ed as it will be interpreted as data to program. the status register p/e.c. bit sr7 should be read to check that the p/e.c. is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to ?1?) and the buffer enhanced factory program operation is terminated. see status register section for details on the error.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 27/114 4.9.2 program and verify phase the program and verify phase requires 32 cycles to program the 32 words to the write buffer. the data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). to prog ram less than 32 words, the remaining words should be programmed with ffffh. three successive steps are required to issue and execute the program and verify phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/e.c. increments the address location.if any address that is not in the same block as the start address is given, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. once the write buffer is full, the data is programmed sequentially to the memory array. after the program operation the device automatically verifies the data and reprograms if necessary. the program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. status register bit sr0 must be checked to determine whether the program operation is finished. the status register may be checked for errors at any time but it must be checked after the entire block has been programmed. 4.9.3 exit phase status register p/e.c. bit sr7 set to ?1? indicates that the device has exited the buffer enhanced factory program operation and returned to read status register mode. a full status register check should be done to ensure that the block has been successfully programmed. see the section on the status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. typical program times are given in ta bl e 1 9 . see appendix c , figure 29: buffer enhanced factory program flowchart and pseudo code , for a suggested flowchart on using the buffer enhanced factory program command.
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 28/114 4.10 program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. the command can be addressed to any bank. the program/erase resume command is required to restart the suspended operation. one bus write cycle is required to issue the program/erase suspend command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of th e status register will be set to ?1?. the following commands are accepted during program/erase suspend: program/erase resume read array (data from erase-suspended block or program-suspended word is not valid) read status register read electronic signature read cfi query. additionally, if the suspended operation was a block erase then the following commands are also accepted: clear status register program (except in erase-suspended block) buffer program (except in erase suspended blocks) block lock block lock-down block unlock. during an erase suspend the block being erased can be protected by issuing the block lock or block lock-down commands. when the program/erase resume command is issued the operation will complete. it is possible to accumulate multiple suspend operations. for example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. if a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. the program/erase suspend command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corresponding data. refer to dual operations section for detailed information about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , goes to v il . see appendix c , figure 24: program suspend & resume flowchart and pseudo code , and figure 26: erase suspend & resume flowchart and pseudo code , for flowcharts for using the program/erase suspend command.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 29/114 4.11 program/erase resume command the program/erase resume command is used to restart the program or erase operation suspended by the program/erase suspend command. one bus write cycle is required to issue the command. the command can be issued to any address. the program/erase resume command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corresponding data. if a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation has completed. see appendix c , figure 24: program suspend & resume flowchart and pseudo code , and figure 26: erase suspend & resume flowchart and pseudo code , for flowcharts for using the program/erase resume command. 4.12 protection register program command the protection register program command is used to program the user one-time- programmable (otp) segments of the protection register and the two protection register locks. the device features 16 otp segments of 128 bits and one otp segment of 64 bits, as shown in figure 5: protection register memory map . the segments are programmed one word at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two bus write cycles are required to issue the protection register program command. the first bus cycle sets up the pr otection register program command. the second latches the address and data to be programmed to the protection register and starts the program/erase controller. read operations to the bank being programmed output the status register content after the program operation has started. attempting to program a previo usly protected protection regist er will result in a status register error. the protection register program cannot be suspended. dual operations between the parameter bank and the protection register memory space are not allowed (see table 17: dual operation limitations for details) the two protection register locks are used to protect the otp segments from further modification. the protection of the otp segments is not reversible. refer to figure 5: protection register memory map2 , and table 9., protection register locks, for details on the lock bits. see appendix c , figure 28: protection register program flowchart and pseudo code , for a flowchart for using the protection register program command.
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 30/114 4.13 set configuration register command the set configuration register command is used to write a new value to the configuration register. two bus write cycles are required to issue the set configuration register command. the first cycle sets up the set configuration register command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. the configuration register data must be written as an address during the bus write cycles, that is adq0 = cr0, adq1 = cr1, ?, adq15 = cr15. addresses a16-amax are ignored. read operations output the array content after the set configuration register command is issued. the read electronic signature command is required to read the updated contents of the configuration register. 4.14 block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked after power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address and locks the block. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 8 shows the lock status after issuing a block lock command. once set, the block lock bits remain set even after a hardware reset or power-down/power- up. they are cleared by a block unlock command. refer to the section, block locking, for a detailed explanation. see appendix c , figure 27: locking operations flowchart and pseudo code , for a flowchart for using the lock command. 4.15 block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address and unlocks the block. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 8 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and appendix c , figure 27: locking operations flowchart and pseudo code , for a flowchart for using the block unlock command.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 31/114 4.16 block lock-down command the block lock-down command is used to lock-down a locked or unlocked block. a locked-down block cannot be programmed or erased. the lock status of a locked-down block cannot be changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock-down command. the second bus write cycle latches the bl ock address and locks-down the block. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta bl e 1 8 shows the lock status after issuing a block lock-down command. refer to the section, block locking, for a detailed explanation and appendix c , figure 27: locking operations flowchart and pseudo code , for a flowchart for using the lock-down command.
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 32/114 table 6. standard commands (1) 1. x = don't care, wa = word address in targeted ban k, rd = read data, srd = status register data, esd = electronic signature data, qd = query data, ba = block addre ss, bka = bank address, pd = program data, pra = protection register address, prd = protection register data, crd = configuration register data. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) 2. must be same bank as in the first cyc le. the signature addresses are listed in table 8 . srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write x 50h block erase 2 write bka or ba (3) 3. any address within the bank can be used. 20h write ba d0h program 2 write bka or wa (3) 40h or 10h write wa pd buffer program (4) 4. n+1 is the number of words to be programmed. n+4 write ba e8h write ba n write pa 1 pd 1 write pa 2 pd 2 write pa n+1 pd n+1 write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka or ba (3) 60h write ba 01h block unlock 2 write bka or ba (3) 60h write ba d0h block lock-down 2 write bka or ba (3) 60h write ba 2fh
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 33/114 table 7. factory program command (1) 1. wa = word address in targeted bank, bka = bank addr ess, pd = program data, ba = block address, x = don?t care. command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data buffer enhanced factory program setup 2 bka or wa (2) 2. any address within the bank can be used. 80h wa 1 d0h program/ verify (3) 3. the program/verify phase can be exec uted any number of times as long as the data is to be programmed to the same block. 32 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 31 wa 1 pd 32 exit 1 not ba 1 (4) 4. wa 1 is the start address, not ba 1 = not block address of wa 1 . x table 8. electronic signature codes code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 882c (m58lr256gu) 882e (M58LR128GU) bottom bank address + 01 882d (m58lr256gl) 882f (m58lr128gl) block protection locked block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 die revision code bank address + 03 drc (1) 1. cr = configuration register, prld = protec tion register lock data, drc = die revision code. configuration register bank address + 05 cr (1) protection register pr0 lock st factory default bank address + 80 0002 otp area permanently locked 0000 protection register pr0 bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 88 otp area protection register pr1 through pr16 lock bank address + 89 prld (1) protection registers pr1-pr16 bank address + 8a bank address + 109 otp area
command interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 34/114 figure 5. protection register memory map ai07563 user programmable otp unique device number protection register lock 1 0 88h 88h 85h 84h 81h 80h user programmable otp protection registers user programmable otp protection register lock 10 432 975 13 12 10 11 8 6 14 15 pr1 pr16 pr0 89h 8ah 91h 102h 109h
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface 35/114 table 9. protection register locks lock description number address bits lock 1 80h bit 0 preprogrammed to protect unique device number, address 81h to 84h in pr0 bit 1 protects 64bits of otp segment, address 85h to 88h in pr0 bits 2 to 15 reserved lock 2 89h bit 0 protects 128bits of otp segment pr1 bit 1 protects 128bits of otp segment pr2 bit 2 protects 128bits of otp segment pr3 ---- ---- bit 13 protects 128bits of otp segment pr14 bit 14 protects 128bits of otp segment pr15 bit 15 protects 128bits of otp segment pr16
status register m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 36/114 5 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register, refer to read status register command section for more details. to output the contents, the status register is latched and up dated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank, always read the status register during program and erase operations operations, if no read array command has been issued. the various bits convey information about the status and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on errors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. the bits in the status register are summarized in table 10: status register bits . refer to ta bl e 1 0 in conjunction with the following text descriptions. 5.1 program/erase controller status bit (sr7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active; when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status bit is low immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is high. 5.2 erase suspend status bit (sr6) the erase suspend status bit indicates that an erase operation has been suspended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase c ontroller inactive). sr6 is set within the erase suspend latency time of the program/erase suspend command being issued therefore the memory may still complete th e operation rather than entering the suspend mode. when a program/erase resume command is issued the erase suspend status bit returns low.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl status register 37/114 5.3 erase status bit (sr5) the erase status bit is used to identify if there was an error during a block erase operation. when the erase status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to th e block and still failed to verify that it has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). once set high, the erase status bit must be set low by a clear status register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail. 5.4 program status bit (sr4) the program status bit is used to identify if there was an error during a program operation. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. attempting to program a '1' to an already programmed bit while v pp = v pph will also set the program status bit high. if v pp is different from v pph , sr4 remains low (set to '0') and the attempt is not shown. once set high, the program status bit must be set low by a clear status register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail. 5.5 v pp status bit (sr3) the v pp status bit is used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. program and erase operations are not guaranteed if v pp becomes invalid during an operation. when the v pp status bit is low (set to ?0?), the voltage on the v pp pin was sampled at a valid voltage. when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and program and erase operations cannot be performed. once set high, the v pp status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
status register m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 38/114 5.6 program suspend status bit (sr2) the program suspend status bit indicates that a program operation has been suspended in the addressed block. the program suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. sr2 is set within the program suspend latency time of the program/erase suspend command being issued therefore the memory ma y still complete the ope ration rather than entering the suspend mode. when a program/erase resume command is issued the program suspend status bit returns low. 5.7 block protection status bit (sr1) the block protection status bit is used to iden tify if a program or block erase operation has tried to modify the contents of a locked or locked-down block. when the block protection status bit is high (set to ?1?), a program or erase operation has been attempted on a locked or locked-down block. once set high, the block protection status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail. 5.8 bank write/multiple word program status bit (sr0) the bank write status bit indicates whether t he addressed bank is programming or erasing. in buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. the bank write status bit should only be considered valid when the program/erase controller status sr7 is low (set to ?0?). when both the program/erase controller status bit and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase controller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in buffer enhanced factory program mode if multiple word program status bit is low (set to ?0?), the device is ready for the next word, if the multiple word program status bit is high (set to ?1?) the device is not ready for the next word. for further details on how to use the status register, see the flowcharts and pseudocodes provided in appendix c .
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl status register 39/114 table 10. status register bits bit name type logic level (1) 1. logic level '1' is high, '0' is low. definition sr7 p/e.c. status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase status error '1' erase error '0' erase success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 bank write status status '1' sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank '0' sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (buffer enhanced factory program mode) status '1' sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next buffer loading or is going to exit the befp mode '0' sr7 = ?1? the device has exited the befp mode sr7 = ?0? the device is ready for the next buffer loading
configuration register m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 40/114 6 configuration register the configuration register is used to configur e the type of bus access that the memory will perform. refer to read modes section for details on read operations. the configuration register is set through the command interface using the set configuration register command. after a reset or power-up the device is configured for asynchronous read (cr15 = 1). the configuration register bits are described in ta b l e 1 2 . they specify the selection of the burst length, burst type, burst x latency and the read operation. refer to figures 6 and 7 for examples of synchronous burst configurations. 6.1 read select bit (cr15) the read select bit, cr15, is used to switch between asynchronous and synchronous read operations. when the read select bit is set to ?1?, read operations are asynchronous; when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is supported in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to ?1? for asynchronous access. 6.2 x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. refer to figure 6: x-latency and data output configuration example . for correct operation the x-latency bits can only assume the values in ta b l e 1 2 : configuration register bits . ta bl e 1 1 shows how to set the x-latency parameter, taking into account the speed class of the device and the frequency used to read the flash memory in synchronous mode. table 11. x-latency settings fmax t k min x-latency min speed 85ns (128mbit) speed 90ns (256mbit) 30mhz 33ns 3 3 40mhz 25ns 3 4 54mhz 19ns 4 5 66mhz 15ns 5 6
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl configuration register 41/114 6.3 wait polarity bit (cr10) the wait polarity bit is used to set the polarity of the wait signal used in synchronous burst read mode. during synchronous burst read mode the wait signal indicates whether the data output are valid or a wait state must be inserted. when the wait polarity bit is set to ?0? the wait signal is active low. when the wait polarity bit is set to ?1? the wait signal is active high. 6.4 data output configuration bit (cr9) the data output configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. when the data output configuration bit is ?0? the output data is valid for one clock cycle, when the data output configuration bit is ?1? the output data is valid for two clock cycles. the data output configuration must be configured using the following condition: t k > t kqv + t qvk_cpu where: t k is the clock period t qvk_cpu is the data setup time required by the system cpu t kqv is the clock to data valid time if this condition is not satisfied, the data outp ut configuration bit should be set to ?1? (two clock cycles). refer to figure 6: x-latency and data output configuration example . 6.5 wait configuration bit (cr8) the wait configuration bit is used to control the timing of the wait output pin, wait, in synchronous burst read mode. when wait is asserted, data is not valid an d when wait is deasserted, data is valid. when the wait configuration bit is low (set to ?0?) the wait output pin is asserted during the wait state. when the wait configuration bit is high (set to ?1?), the wait output pin is asserted one data cycle before the wait state. 6.6 burst type bit (cr7) the burst type bit determines the sequence of addresses read during synchronous burst reads. the burst type bit is high (set to ?1?), as the memory outputs from sequential addresses only. see table 13: burst type definition , for the sequence of addresses output from a given starting address in sequential mode.
configuration register m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 42/114 6.7 valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to configure the active edge of the clock, k, during synchronous read operations. wh en the valid clock edge bit is low (set to ?0?) the falling edge of the clock is the active edge. when the valid clock edge bit is high (set to ?1?) the rising edge of the clock is the active edge. 6.8 wrap burst bit (cr3) the wrap burst bit, cr3, is used to select between wrap and no wrap. synchronous burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). when the wrap burst bit is low (set to ?0?) the burst read wraps. when it is high (set to ?1?) the burst read does not wrap. 6.9 burst length bits (cr2-cr0) the burst length bits are used to set the number of words to be output during a synchronous burst read operation as re sult of a single address latch cycle. they can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the wait signal to indicate that a delay is necessary before the data is output. if the starting address is aligned to an 8 word boundary no wait states are needed and the wait output is not asserted. if the starting address is not aligned to the 8 wo rd boundary, wait will be asserted when the burst sequence crosses the first 16 word boundary to indicate that the device needs an internal delay to read the successive words in the array. in the worst case, the number of wait states is one clock cycle less than the latency setting. the exact number is reported in table 14: wait at the boundary . wait will be asserted only once during a continuous burst access. see also section table 13.: burst type definition . cr14, cr5 and cr4 are reserved for future use.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl configuration register 43/114 table 12. configuration register bits bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x-latency 010 2 clock latency (1) 1. the combination x-latency=2, data held for two cloc k cycles and wait active one data cycle before the wait state is not supported. 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) other configurations reserved cr10 wait polarity 0 wait is active low (default) 1 wait is active high cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) (1) cr8 wait configuration 0 wait is active duri ng wait state (default) 1 wait is active one data cycle before wait state (1) cr7 burst type 0reserved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5-cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 011 16 words 111 continuous (default)
configuration register m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 44/114 table 13. burst type definition mode start add. sequential continuous burst 4 words 8 words 16 words wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12- 13-14-15 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13- 14-15-0 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13- 14-15-0-1 2-3-4-5-6-7-8... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14- 15-0-1-2 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2- 3-4-5-6 7-8-9-10-11-12-13... ... 12 12-13-14-15 12-13-14-15-8-9- 10-11 12-13-14-15-0-1-2-3-4-5-6-7-8- 9-10-11 12-13-14-15-16- 17... 13 13-14-15-12 13-14-15-8-9-10- 11-12 13-14-15-0-1-2-3-4-5-6-7-8-9- 10-11-12 13-14-15-16-17- 18... 14 14-15-12-13 14-15-8-9-10-11- 12-13 14-15-0-1-2-3-4-5-6-7-8-9-10- 11-12-13 14-15-16-17-18- 19... 15 15-12-13-14 15-8-9-10-11-12- 13-14 15-0-1-2-3-4-5-6-7-8-9-10-11- 12-13-14 15-16-17-18-19- 20... no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12- 13-14-15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8--9-10-11-12-13- 14-15-16 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5--6-7-8-9-10-11-12-13- 14-15-16-17 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14- 15-16-17-18 ... 7 7-8-9-10 7-8-9-10-11-12- 13-14 7-8-9-10-11-12-13-14-15-16- 17-18-19-20-21-22 ... 12 12-13-14-15 12-13-14-15-16- 17-18-19 12-13-14-15-16-17-18-19-20- 21-22-23-24-25-26-27 13 13-14-15-16 13-14-15-16-17- 18-19-20 13-14-15-16-17-18-19-20-21- 22-23-24-25-26-27-28 14 14-15-16-17 14-15-16-17-18- 19-20-21 14-15-16-17-18-19-20-21-22- 23-24-25-26-27-28-29 15 15-16-17-18 15-16-17-18-19- 20-21-22 15-16-17-18-19-20-21-22-23- 24-25-26-27-28-29-30
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl configuration register 45/114 figure 6. x-latency and data output configuration example 1. amax is equal to a22 for the m58lr 128gu/l and to a23 for the m58lr256gu/l. 2. the settings shown are x-latency = 4, data output held for one clock cycle. table 14. wait at the boundary start address number of wait states x-latency = 7 x-latency = 6 x-latency = 5 x-latency = 4 x-latency = 3 x-latency = 2 0000000 1000000 2100000 3210000 4321000 5432100 6543210 7654321 ai10977 amax-a16 (1) valid address k l adq15-adq0 valid data x-latency valid data tk tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle e valid address
configuration register m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 46/114 figure 7. wait configuration example 1. amax is equal to a22 for the m58lr 128gu/l and to a23 for the m58lr256gu/l. ai10091 amax-a16 (1) valid address k l adq15-adq0 valid address valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1' g
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl read modes 47/114 7 read modes read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is ?don?t care? for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see configuration register section for details). all banks support both asynchronous and synchronous read operations. 7.1 asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corresponding to the address latched, th at is the memory array, status register, common flash interface or electronic signat ure depending on the command issued. cr15 in the configuration register must be set to ?1? for asynchronous operations. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. in asynchronous read mode, the wait signal is always deasserted. see table 25: asynchronous read ac characteristics , figure 10: asynchronous random access read ac waveforms , for details.
read modes m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 48/114 7.2 synchronous burst read mode in synchronous burst read mode the data is output in bursts synchronized with the clock. it is possible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read operations, such as read status register, read cfi and read electronic signature, single synchronous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are configured in the configuration register. a burst sequence starts at the first clock ed ge (rising or falling dep ending on valid clock edge bit cr6 in the configuration register) afte r the falling edge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and data is output on each data cycle after a delay which depends on the x latency bits cr13-cr11 of the configuration register. the number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output configuration bit cr9). the order of the data output can be modified through the wrap burst bit in the configuration register. the burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). the wait signal may be asserted to indicate to the system that an ou tput delay will occur. this delay will depend on the starting address of the bu rst sequence and on the burst configuration. wait is asserted during the x latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only deasserted when output data are valid or when g is at v ih . in continuous burst read mode a wait state will occur when crossing the fi rst 16 word boundary. if the starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. the wait signal can be configured to be active low or active high by setting cr10 in the configuration register. see table 26: synchronous read ac characteristics , and figure 11: synchronous burst read ac waveforms , for details.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl read modes 49/114 7.2.1 synchronous burst read suspend a synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. it can be suspended during the initial access latency time (before data is output), or after the device has output data. when the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be su spended and resumed as often as required as long as the operating conditions of the device are met. a synchronous burst read operation is suspended when chip enable, e , is low and the current address has been latched (on a latch enable rising edge or on a valid clock edge). the clock signal is then halted at v ih or at v il , and output enable, g , goes high. when output enable, g , becomes low again and the clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. wait being gated by e , it will remain active and will no t revert to high impedance when g goes high. so if two or more devices are connected to the system?s ready signal, to prevent bus contention the wait signal of the m58lrxxxgu/l should not be directly connected to the system?s ready signal. wait will revert to high-impedance when chip enable, e , goes high. see table 26: synchronous read ac characteristics , and figure 13: synchronous burst read suspend ac waveforms , for details. 7.3 single synchronous read mode single synchronous read operations are sim ilar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is deasserted when output enable, g , is at v ih or for the one clock cycle during which output data is va lid. otherwise, it is asserted. see table 26: synchronous read ac characteristics , and figure 11: synchronous burst read ac waveforms , for details.
dual operations and multiple bank architecture m58lr256gu, m58lr256gl, M58LR128GU, 50/114 8 dual operations and multiple bank architecture the multiple bank arch itecture of the m58lr xxxgu/l gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one programming and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. by using a combination of these features, read operations are possible at any moment in the m58lrxxxgu/l device. dual operations between the parameter bank and either of the cfi, the otp or the electronic signature memory space are not allowed. ta bl e 1 7 shows which dual operations are allowed or not between the cfi, the otp, the electronic signature locations and the memory array. ta bl e s 15 and 16 show the dual operations possible in other banks and in the same bank. table 15. dual operations allowed in other banks status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program, buffer program block erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s p r o g r a m m i n g ye s ye s ye s ye s ? ? ye s ? erasing yes yes yes yes ? ? yes ? program suspended yes yes yes yes ? ? ? yes erase suspended ye s ye s ye s ye s ye s ? ? ye s
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dual operations and multiple bank ar- 51/114 table 16. dual operations allowed in same bank status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program, buffer program block erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming ? (1) 1. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. ye s ye s ye s ? ? ye s ? erasing ? (1) ye s ye s ye s ? ? ye s ? program suspended ye s (2) 2. not allowed in the word that is being erased or programmed. ye s ye s ye s ? ? ? ye s erase suspended ye s (2) ye s ye s ye s ye s (2) ??yes table 17. dual operation limitations current status commands allowed read cfi / otp / electronic signature read parameter blocks read main blocks located in parameter bank not located in parameter bank programming / erasing parameter blocks no no no yes programming / erasing main blocks located in parameter bank ye s n o n o ye s not located in parameter bank ye s ye s ye s in different bank only programming otp no no no no
block locking m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 52/114 9 block locking the m58lrxxxgu/l features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows software only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and locked-down. ta bl e 1 8 , defines all of the possible protection states (wp , adq1, adq0), and appendix c , figure 27 , shows a flowchart for the locking operations. 9.1 reading a block?s lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode issue the read electronic signature command. subsequent reads at the address specified in ta bl e 8 , will output the protection status of that block. the lock status is represented by adq0 and adq1. adq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. adq0 is automatically set when entering lock-down. adq1 indicates the lock-down status and is set by the lock-down command. adq1 cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. 9.2 locked state the default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from program or erase operations. any program or erase operations attempted on a lo cked block will return an error in the status register. the status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. 9.3 unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by issuing the unlock command.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl block locking 53/114 9.4 lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked-down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the write protect, wp , input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. when the lock-down function is disabled (wp =1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. when wp =0 blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes that were made while wp =1. device reset or power-down resets all blocks, including those in lock-down, to the locked state. 9.5 locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after completing any desired lock, read, or pr ogram operations, resume the erase operation with the erase resume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend.
block locking m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 54/114 table 18. lock status current protection status (1) (wp , adq1, adq0) 1. the lock status is defined by the write protect pin and by adq1 (?1? for a locked-down block) and adq0 (?1? for a locked block) as read in the read electronic signature command with adq1 = v ih and adq0 = v il . next protection status (1) (wp , adq1, adq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) 2. all blocks are locked at power-up, so the de fault configuration is 001 or 101 according to wp status. no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1 ,1 1,1,1 or 1,1,0 (3) 3. a wp transition to v ih on a locked block will restore the pr evious adq0 value, giving a 111 or 110.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl program and erase times and endur- 55/114 10 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 1 9 exact erase times may change depending on the memory array condition. the best case is when all the bits in the block are at ?0? (pre-programmed). the worst case is when all the bits in the block are at ?1? (not preprogrammed). usually, the system overhead is negligible with respect to the erase time. in the m58lrxxxgu/l the maximum number of program/erase cycles depends on the v pp voltage supply used. table 19. program/erase times and endurance cycles (1) (2) parameter condition min typ typical after 100kw/e cycles max unit v pp = v dd erase parameter block (16 kword) 0.4 1 2.5 s main block (64 kword) preprogrammed 1 3 4 s not preprogrammed 1.2 4 s program (3) single cell word program 30 60 s buffer program 30 60 s single word word program 90 180 s buffer program 90 180 s buffer (32 words) (buffer program) 440 880 s main block (64 kword) 880 ms suspend latency program 20 25 s erase 20 25 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v pp = v pph erase parameter block (16 kword) 0.4 2.5 s main block (64 kword) 1 4 s program (3) single word word program 85 170 s buffer enhanced factory program (4) 10 s buffer (32 words) buffer program 340 680 s buffer enhanced factory program 320 s main block (64 kwords) buffer program 640 ms buffer enhanced factory program 640 ms bank (16 mbits) buffer program 10 s buffer enhanced factory program 10 s program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles 1. t a = ?25 to 85c; v dd = 1.7v to 2v; v ddq = 1.7v to 2v. 2. values are liable to change with t he external system-level overhead (command sequence and status register polling execution). 3. excludes the time needed to execute the command sequence. 4. this is an average value on the entire device.
maximum rating m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 56/114 11 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 20. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?65 125 c v io input or output voltage ?0.5 3.8 v v dd supply voltage ?0.2 2.5 v v ddq input/output supply voltage ?0.2 2.5 v v pp program voltage ?0.2 10 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 57/114 12 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 21: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 8. ac measurement i/o waveform table 21. operating and ac measurement conditions parameter M58LR128GU/l m58lr256gu/l units 85 90 min max min max v dd supply voltage 1.7 2.0 1.7 2.0 v v ddq supply voltage 1.7 2.0 1.7 2.0 v v pp supply voltage (factory environment) 8.5 9.5 8.5 9.5 v v pp supply voltage (application environment) ?0.4 v ddq +0.4 ?0.4 v ddq +0.4 v ambient operating temperature ?25 85 ?25 85 c load capacitance (c l )3030pf input rise and fall times 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 58/114 figure 9. ac measurement load circuit table 22. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6 8 pf c out output capacitance v out = 0v 8 12 pf ai06162 v ddq c l c l includes jig capacitance 16.7k ? device under test 0.1f v dd 0.1f v ddq 16.7k ?
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 59/114 table 23. dc characteristics - currents symbol parameter test condition typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=5mhz) e = v il , g = v ih 13 15 ma supply current synchronous read (f=66mhz) 4 word 18 20 ma 8 word 20 22 ma 16 word 25 27 ma continuous 28 30 ma i dd2 supply current (reset) rp = v ss 0.2v m58lr256gu/l 50 110 a M58LR128GU/l 25 70 i dd3 supply current (standby) e = v dd 0.2v k=v ss m58lr256gu/l 50 110 a M58LR128GU/l 25 70 i dd4 supply current (automatic standby) e = v il , g = v ih m58lr256gu/l 50 110 a M58LR128GU/l 25 70 i dd5 (1) 1. sampled only, not 100% tested. supply current (program) v pp = v pph 820ma v pp = v dd 10 25 ma supply current (erase) v pp = v pph 820ma v pp = v dd 10 25 ma i dd6 (1), (2) 2. v dd dual operation current is the sum of read and program or erase currents. supply current (dual operations) program/erase in one bank, asynchronous read in another bank 23 40 ma program/erase in one bank, synchronous read (continuous f=66mhz) in another bank 38 55 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2v k=v ss m58lr256gu/l 50 110 a M58LR128GU/l 25 70 i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 60/114 table 24. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage 0 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1.3 1.8 3.3 v v pph v pp program voltage factory program, erase 8.5 9.0 9.5 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1 v v rph rp pin extended high voltage 3.3 v
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 61/114 figure 10. asynchronous random access read ac waveforms ai10092 tavav tehqx tglqv tglqx tghqx e g telqv tehqz tghqz adq0-adq15 valid address valid l tellh tllqv tlllh tavlh tlhax wait (1) teltv tehtz notes: 1- write enable, w, is high, wait is active low. 2- a max is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l. valid address latch outputs enabled data valid standby tlhgl hi-z valid address tavqv hi-z a16-amax (2) valid data
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 62/114 table 25. asynchronous read ac characteristics symbol alt parameter M58LR128GU/l m58lr256gu/l unit 85 90 read timings t avav t rc address valid to next address valid min 85 90 ns t avqv t acc address valid to output valid (random) max 85 90 ns t eltv chip enable low to wait valid max 11 11 ns t elqv (1) t ce chip enable low to output valid max 85 90 ns t ehtz chip enable high to wait hi-z max 14 14 ns t ehqx (2) t oh chip enable high to output transition min 0 0 ns t ehqz (2) t hz chip enable high to output hi-z max 14 14 ns t glqv (2) t oe output enable low to output valid max 25 25 ns t glqx (2) t olz output enable low to output transition min 0 0 ns t ghqx (2) t oh output enable high to output transition min 0 0 ns t ghqz (2) t df output enable high to output hi-z max 14 14 ns latch timings t avlh t avadvh address valid to latch enable high min 7 7 ns t ellh t eladvh chip enable low to latch enable high min 10 10 ns t lhax t advhax latch enable high to address transition min 7 7 ns t lllh t advladvh latch enable pulse width min 7 7 ns t llqv t advlqv latch enable low to output valid (random) max 85 90 ns t lhgl t advhgl latch enable high to output enable low min 7 7 ns 1. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 2. sampled only, not 100% tested.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 63/114 figure 11. synchronous burst read ac waveforms ai10093 adq0-adq15 e g a16-amax (4) l wait k valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtv tehqx tehqz tghqx tghqz tkhtx hi-z valid note 2 teltv tehtz address latch x latency valid data flow boundary crossing standby note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. a max is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l. tehel valid address tgltv tglqv
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 64/114 figure 12. single synchronous read ac waveforms ai10094 adq0-adq15 e g a16-amax (4) l wait (2) k (3) valid not valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz hi-z not valid teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. a max is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l. not valid tglqx tehel tkhtv valid address tghtv tgltv
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 65/114 figure 13. synchronous burst read suspend ac waveforms ai10095 adq0-adq15 e g a16-amax (5) l wait (2) k (4) valid valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax valid valid note 1 tehqx tehqz tghqx tghqz hi-z teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. the clock signal can be held high or low 4. address latched and data output on the rising clock edge. 5. a max is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l tglqx tehel valid address tghqz tglqv note 3 tgltv
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 66/114 figure 14. clock input ac waveform 1. sampled only, not 100% tested. 2. for other timings please refer to table 25: asynchronous r ead ac characteristics table 26. synchronous read ac characteristics symbol alt parameter M58LR128GU/l, m58lr256gu/l unit synchronous read timings t avkh t avclkh address valid to clock high min 5 ns t elkh t elclkh chip enable low to clock high min 6 ns t eltv chip enable low to wait valid max 11 ns t ehel chip enable pulse width (subsequent synchronous reads) min 14 ns t ehtz chip enable high to wait hi-z max 14 ns t ghtv output enable high to wait valid min 11 ns t gltv output enable low to wait valid max 11 ns t khax t clkhax clock high to address transition min 7 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 11 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 3 ns t llkh t advlclkh latch enable low to clock high min 5 ns clock specifications t khkh t clk clock period (f=66mhz) min 15 ns t khkl t klkh clock high to clock low clock low to clock high min 3.5 ns t f t r clock fall or rise time max 3 ns ai06981 tkhkh tf tr tkhkl tklkh
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 67/114 figure 15. write ac waveforms, write enable controlled ai11075 adq0-adq15 l g bank add. a16-amax (1) e tlllh w bank address wp v pp tavav command valid add. status register tavav valid add. cmd or data valid address valid address tlhax tavlh tellh tghll tlhgl tellh telqv twlwh telwl twheh twhdx tdvwh twhwl twhel tvphwh twphwh twhwpl tqvwpl twhvpl tqvvpl status register read 1 st polling twhll confirm command set-up command k program or erase note1. a max is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l.
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 68/114 1. t whel has the values shown when reading in the targeted bank or when reading following a set configuration register command.system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing any command and to del ay the first read to any address after issuing a set configuration register command. if the fi rst read after the command is a read array operation in a different bank and no changes to the configuration register have been issued, t whel is 0ns. 2. sampled only, not 100% tested. table 27. write ac characteristics, write enable controlled symbol alt parameter M58LR128GU/l m58lr256gu/l unit 85 90 write enable controlled timings t avav t wc address valid to next address valid min 85 90 ns t avlh address valid to latch enable high min 9 9 ns t dvwh t ds data valid to write enable high min 40 40 ns t ellh chip enable low to latch enable high min 10 10 ns t elwl t cs chip enable low to write enable low min 0 0 ns t elqv chip enable low to output valid min 85 90 ns t ghll output enable high to latch enable low min 20 20 ns t lhax latch enable high to address transition min 9 9 ns t lhgl latch enable high to output enable low min 9 9 ns t lllh latch enable pulse width min 9 9 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whel (2) write enable high to chip enable low min 25 25 ns t whll write enable high to latch enable low min 0 0 ns t whwl t wp h write enable high to write enable low min 25 25 ns t wlwh t wp write enable low to write enable high min 50 50 ns protection timings t qvvpl output (status register) valid to v pp low min 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 ns t vphwh t vps v pp high to write enable high min 200 200 ns t whvpl write enable high to v pp low min 200 200 ns t whwpl write enable high to write protect low min 200 200 ns t wphwh write protect high to write enable high min 200 200 ns
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 69/114 figure 16. write ac waveforms, chip enable controlled ai11076 adq0-adq15 l g bank add a16-amax (1) e tlllh w bank address wp v pp tavav command valid add status register tavav valid add cmd or data valid address valid address tlhax tavlh tellh tghll tlhgl tellh telqv teleh tehel tehdx tdveh twhel tvpheh twpheh tehwpl tqvwpl tehvpl tqvvpl status register read 1 st polling tehll confirm command set-up command k program or erase twlel tehwh note1. a max is equal to a23 in the m58lr256gu/l and to a22 in the M58LR128GU/l.
dc and ac parameters m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 70/114 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank or when reading following a set configuration register command.system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing any command and to del ay the first read to any address after issuing a set configuration register command. if the fi rst read after the command is a read array operation in a different bank and no changes to the configuration register have been issued, t whel is 0ns. table 28. write ac characteristics, chip enable controlled symbol alt parameter M58LR128GU/l m58lr256gu/l unit 85 90 chip enable controlled timings t avav t wc address valid to next address valid min 85 90 ns t avlh address valid to latch enable high min 9 9 ns t dveh t ds data valid to chip enable high min 40 40 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehel t wph chip enable high to chip enable low min 25 25 ns t ehll chip enable high to latch enable low min 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 ns t eleh t wp chip enable low to chip enable high min 50 50 ns t ellh chip enable low to latch enable high min 10 10 ns t elqv chip enable low to output valid min 85 90 ns t ghll output enable high to latch enable low min 20 20 ns t lhax latch enable high to address transition min 9 9 ns t lhgl latch enable high to output enable low min 9 9 ns t lllh latch enable pulse width min 9 9 ns t whel (2) write enable high to chip enable low min 25 25 ns t wlel t cs write enable low to chip enable low min 0 0 ns protection timings t ehvpl chip enable high to v pp low min 200 200 ns t ehwpl chip enable high to write protect low min 200 200 ns t qvvpl output (status register) valid to v pp low min 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 ns t vpheh t vps v pp high to chip enable high min 200 200 ns t wpheh write protect high to chip enable high min 200 200 ns
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl dc and ac parameters 71/114 figure 17. reset and power-up ac waveforms ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll table 29. reset and power-up ac characteristics symbol parameter test condition M58LR128GU/l m58lr256gu/l unit 85 90 t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 25 25 s during erase min 25 25 s other conditions min 85 90 ns t phwl t phel t phgl t phll reset high to write enable low chip enable low output enable low latch enable low min 30 30 ns t plph (1),(2) rp pulse width min 50 50 ns t vdhph (3) supply voltages high to reset high min 100 100 s 1. the device reset is possible but not guaranteed if t plph < 50ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset.
package mechanical m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 72/114 13 package mechanical in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 18. vfbga44 8 10mm - 10 4 ball array, 0.50mm pitch, bottom view package outline 1. drawing is not to scale. a2 a1 bga-z54 d d1 fd1 b e e1 ddd sd se fe a ball "a1" e2 d2 fd fe1 e
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl package mechanical 73/114 table 30. vfbga44 8 10mm - 10 4 ball array, 0.50mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.000 0.0394 a1 0.150 0.0059 a2 0.660 0.0260 b 0.300 0.250 0.350 0.0118 0.0098 0.0138 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 4.500 0.1772 d2 6.500 0.2559 ddd 0.080 0.0031 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 1.500 0.0591 e2 3.500 0.1378 e 0.500 ? ? 0.0197 ? ? fd 1.750 0.0689 fd1 0.750 0.0295 fe 4.250 0.1673 fe1 3.250 0.1280 sd 0.250 0.0098 se 0.250 0.0098
package mechanical m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 74/114 figure 19. vfbga44 7.7 9mm - 10 4 ball array, 0.50mm pitch, bottom view package outline 1. drawing is not to scale. a2 a1 bga-z47 d d1 fd1 b e e1 ddd sd se fe a ball "a1" e2 d2 fd fe1 e
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl package mechanical 75/114 table 31. vfbga44 7.7 9mm - 10 4 ball array, 0.50mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.00 0.039 a1 0.15 0.006 a2 0.66 0.026 b 0.32 0.27 0.37 0.013 0.011 0.015 d 7.70 7.60 7.80 0.303 0.299 0.307 d1 4.50 0.177 d2 6.50 0.256 ddd 0.08 0.003 e 9.00 8.90 9.10 0.354 0.350 0.358 e1 1.50 0.059 e2 3.50 0.138 e0.50? ?0.020? ? fd 1.60 0.063 fd1 0.60 0.024 fe 3.75 0.148 fe1 2.75 0.108 sd 0.25 ? ? 0.010 ? ? se 0.25 ? ? 0.010 ? ?
package mechanical m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 76/114 figure 20. vfbga44 daisy chain - package connections (top view through package) ai08181 h g 6 5 4 3 d c e f a b 12 78 13 12 11 10 914
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl package mechanical 77/114 figure 21. vfbga44 daisy chain - pcb connection proposal (top view through package) end point start point ai08182 h g 6 5 4 3 d c e f a b 12 78 13 12 11 10 914
part numbering m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 78/114 14 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.), for daisy chain ordering information, or for further information on any aspect of this device, please contact the st sales office nearest to you. table 32. ordering information scheme example: m58lr256gu 90 zc 5 e device type m58 architecture l = multi-level, multiple bank, burst mode operating voltage r = v dd = 1.7v to 2.0v, v ddq = 1.7v to 2.0v density 128 = 128 mbit (x16) 256 = 256 mbit (x16) technology g = 0.13m technology multi-level design parameter location u = top boot, mux i/o l = bottom boot, mux i/o speed 85 = 85ns (M58LR128GU/l) 90 = 90ns (m58lr256gu/l) package zc = vfbga44, 8 x 10mm, 0.50mm pitch (m58lr256gu/l only) zb = vfbga44, 7.7 x 9mm, 0.50mm pitch (M58LR128GU/l only) temperature range 5 = ?25 to 85c packing option e = ecopack? package, standard packing u = ecopack? package, tape & reel packing, 16mm
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl block address tables 79/114 appendix a block address tables the following set of equations can be used to calculate a complete set of block addresses for the m58lrxxxgu/l using the information contained in tables 33 to 44 . to calculate the block base address from the block number: first it is necessary to calculate the bank number and the block number offset. this can be achieved using the following formulas: bank_number = (block_number ? 3) / num_blocks_in_a_main_bank block_number_offset = block_number ? 3 ? (bank_number x num_blocks_in_a_main_bank), where num_blocks_in_a_main_bank is equal to 8 for the m58lr256gu/l and to 16 for the M58LR128GU/l. if bank_number = 0, the block base address can be directly read from tables 33 and 36 for the m58lr256gu/l or tables 39 and 42 for the M58LR128GU/l (parameter bank block addresses) in the address range column, in the row that corresponds to the given block number. otherwise: block_base_address = bank_base_address + block_base_address_offset to calculate the bank number and the block number from the block base address: if the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from tables 33 and 36 for the m58lr256gu/l or tables 39 and 42 for the M58LR128GU/l (parameter bank block addresses), in the block number column, in the row that corresponds to the address given. otherwise, the block number can be calculated using the formulas below: for the top configuration (m58lrxxxgu): block_number = ((not address) / 2 16 ) + 3 for the bottom configuration (m58lrxxxgl): block_number = (address / 2 16 ) + 3 for both configurations the bank number and the block number offset can be calculated using the following formulas: bank_number = (block_number ? 3) / num_blocks_in_a_main_bank block_number_offset = block_number ? 3 ? (bank_number x num_blocks_in_a_main_bank) where num_blocks_in_a_main_bank is equal to 8 for the m58lr256gu/l and to 16 for the M58LR128GU/l.
block address tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 80/114 table 33. m58lr256gu - parameter bank block addresses block number size (kwords) address range 0 16 ffc000-ffffff 1 16 ff8000-ffbfff 2 16 ff4000-ff7fff 3 16 ff0000-ff3fff 4 64 fe0000-feffff 5 64 fd0000-fdffff 6 64 fc0000-fcffff 7 64 fb0000-fbffff 8 64 fa0000-faffff 9 64 f90000-f9ffff 10 64 f80000-f8ffff 11 64 f70000-f7ffff 12 64 f60000-f6ffff 13 64 f50000-f5ffff 14 64 f40000-f4ffff 15 64 f30000-f3ffff 16 64 f20000-f2ffff 17 64 f10000-f1ffff 18 64 f00000-f0ffff
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl block address tables 81/114 table 34. m58lr256gu - main bank base addresses bank number (1) 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 1 19-34 e00000 2 35-50 d00000 3 51-66 c00000 4 67-82 b00000 5 83-98 a00000 6 99-114 900000 7 115-130 800000 8 131-146 700000 9 147-162 600000 10 163-178 500000 11 179-194 400000 12 195-210 300000 13 211-226 200000 14 227-242 100000 15 243-258 000000 table 35. m58lr256gu - block addresses in main banks block number offset bl ock base address offset 0 0f0000 1 0e0000 2 0d0000 3 0c0000 4 0b0000 5 0a0000 6 090000 7 080000 8 070000 9 060000 10 050000 11 040000 12 030000 13 020000 14 010000 15 000000
block address tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 82/114 table 36. m58lr256gl - parameter bank block addresses block number size (kwords) address range 18 64 0f0000-0fffff 17 64 0e0000-0effff 16 64 0d0000-0dffff 15 64 0c0000-0cffff 14 64 0b0000-0bffff 13 64 0a0000-0affff 12 64 090000-09ffff 11 64 080000-08ffff 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl block address tables 83/114 table 37. m58lr256gl - main bank base addresses bank number (1) 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 15 243-258 f00000 14 227-242 e00000 13 211-226 d00000 12 195-210 c00000 11 179-194 b00000 10 163-178 a00000 9 147-162 900000 8 131-146 800000 7 115-130 700000 6 99-114 600000 5 83-98 500000 4 67-82 400000 3 51-66 300000 2 35-50 200000 1 19-34 100000 table 38. m58lr256gl - block addresses in main banks block number offset bl ock base address offset 15 0f0000 14 0e0000 13 0d0000 12 0c0000 11 0b0000 10 0a0000 9 090000 8 080000 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000
block address tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 84/114 table 39. M58LR128GU - parameter bank block addresses block number size (kwords) address range 0 16 7fc000-7fffff 1 16 7f8000-7fbfff 2 16 7f4000-7f7fff 3 16 7f0000-7f3fff 4 64 7e0000-7effff 5 64 7d0000-7dffff 6 64 7c0000-7cffff 7 64 7b0000-7bffff 8 64 7a0000-7affff 9 64 790000-79ffff 10 64 780000-78ffff table 40. M58LR128GU - main bank base addresses bank number (1) 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 1 11-18 700000 2 19-26 680000 3 27-34 600000 4 35-42 580000 5 43-50 500000 6 51-58 480000 7 59-66 400000 8 67-74 380000 9 75-82 300000 10 83-90 280000 11 91-98 200000 12 99-106 180000 13 107-114 100000 14 115-122 080000 15 123-130 000000
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl block address tables 85/114 table 41. M58LR128GU - block addresses in main banks block number offset block base address offset 0 070000 1 060000 2 050000 3 040000 4 030000 5 020000 6 010000 7 000000 table 42. m58lr128gl - parameter bank block addresses block number size (kwords) address range 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff
block address tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 86/114 table 43. m58lr128gl - main bank base addresses bank number (1) 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 15 123-130 780000 14 115-122 700000 13 107-114 680000 12 99-106 600000 11 91-98 580000 10 83-90 500000 9 75-82 480000 8 67-74 400000 7 59-66 380000 6 51-58 300000 5 43-50 280000 4 35-42 200000 3 27-34 180000 2 19-26 100000 1 11-18 080000 table 44. m58lr128gl - block addresses in main banks block number offset block base address offset 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl common flash interface 87/114 appendix b common flash interface the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 and 54 show the addresses used to retrieve the data. the query data is always presented on the lowest order data outputs (adq0-adq7), the other outputs (adq8-adq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is written (see figure 5., protection register memory map). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by st. issue a read array command to return to read mode. table 45. query structure overview (1) 1. the flash memory display the cfi data structure w hen cfi query command is issued. in this table are listed the main sub-sections detailed in tables 46 , 47 , 48 and 49 . query data is always presented on the lowest order data outputs. offset sub-section name description 000h reserved reserved for algorithm-specific information 010h cfi query identification string command set id and algorithm data offset 01bh system interface information dev ice timing & voltage information 027h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 080h security code area lock protection register unique device number and user programmable otp
common flash interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 88/114 table 46. cfi query identification string offset sub-section name description value 000h 0020h manufacturer code st 001h 882ch 882eh 882dh 882fh device code m58lr256gu M58LR128GU m58lr256gl m58lr128gl to p to p bottom bottom 002h reserved reserved 003h drc die revision code 004h- 00fh reserved reserved 010h 0051h query unique ascii string "qry" "q" 011h 0052h "r" 012h 0059h "y" 013h 0001h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 014h 0000h 015h offset = p = 000ah address for primary algorithm extended query table (see ta bl e 4 9 ) p = 10ah 016h 0001h 017h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 018h 0000h 019h value = a = 0000h address for alternate algorithm extended query table na 01ah 0000h
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl common flash interface 89/114 table 47. cfi query system interface information offset data description value 01bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 01ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 01dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5v 01eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5v 01fh 0008h typical time-out per single byte/word program = 2 n s 256s 020h 0009h typical time-out for buffer program = 2 n s 512s 021h 000ah typical time-out per individual block erase = 2 n ms 1s 022h 0000h typical time-out for full chip erase = 2 n ms na 023h 0001h maximum time-out for word program = 2 n times typical 512s 024h 0001h maximum time-out for buffer program = 2 n times typical 1024s 025h 0002h maximum time-out per individual block erase = 2 n times typical 4s 026h 0000h maximum time-out for chip erase = 2 n times typical na
common flash interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 90/114 table 48. device geometry definition offset data description value 027h 0019h m58lr256gu/l device size = 2 n in number of bytes 32 mbytes 0018h M58LR128GU/l device size = 2 n in number of bytes 16 mbytes 028h 029h 0001h 0000h flash device interface code description x16 async. 02ah 02bh 0006h 0000h maximum number of bytes in multi-byte program or page = 2 n 64 bytes 02ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 top devices 02dh 02eh 00feh 0000h m58lr256gu/l erase block region 1 information number of identical-size erase blocks = 00feh+1 255 007eh 0000h M58LR128GU/l erase block region 1 information number of identical-size erase blocks = 007eh+1 127 02fh 030h 0000h 0002h erase block region 1 information block size in region 1 = 0200h * 256 byte 128 kbyte 031h 032h 0003h 0000h erase block region 2 information number of identical-size erase blocks = 0003h+1 4 033h 034h 0080h 0000h erase block region 2 information block size in region 2 = 0080h * 256 byte 32 kbyte 035h 038h reserved reserved for future erase block region information na bottom devices 02dh 02eh 0003h 0000h erase block region 1 information number of identical-size erase block = 0003h+1 4 02fh 030h 0080h 0000h erase block region 1 information block size in region 1 = 0080h * 256 bytes 32 kbytes 031h 032h 00feh 0000h m58lr256gu/l erase block region 2 information number of identical-size erase block = 00feh+1 255 007eh 0000h M58LR128GU/l erase block region 2 information number of identical-size erase block = 007eh+1 127 033h 034h 0000h 0002h erase block region 2 information block size in region 2 = 0200h * 256 bytes 128 kbytes 035h 038h reserved reserved for future erase block region information na
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl common flash interface 91/114 table 49. primary algorithm-specific extended query table offset data description value (p)h = 10ah 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h =10dh 0031h major version number, ascii "1" (p+4)h = 10eh 0033h minor version number, ascii "3" (p+5)h = 10fh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported(1 = yes, 0 = no) bit 1 erase suspend supported(1 = yes, 0 = no) bit 2 program suspend supported(1 = yes, 0 = no) bit 3 legacy lock/unlock supported(1 = yes, 0 = no) bit 4 queued erase supported(1 = yes, 0 = no) bit 5 instant individual block locking supported(1 = yes, 0 = no) bit 6 protection bits supported(1 = yes, 0 = no) bit 7 page mode read supported(1 = yes, 0 = no) bit 8 synchronous read supported(1 = yes, 0 = no) bit 9 simultaneous operation supported(1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 111h 0000h (p+8)h = 112h 0000h (p+9)h = 113h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are ?0? ye s (p+a)h = 114h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = ye s , 0 = n o ) bit 15 to 2 reserved for future use; undefined bits are ?0? ye s ye s (p+b)h = 115h 0000h (p+c)h = 116h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8v (p+d)h = 117h 0090h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9v
common flash interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 92/114 table 50. protection register information offset data description value (p+e)h = 118h 0002h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 2 (p+f)h = 119h 0080h protection fi eld 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 80h (p+10)h = 11ah 0000h 00h (p+ 11)h = 11bh 0003h 8 bytes (p+12)h = 11ch 0003h 8 bytes (p+13)h = 11dh 0089h protection register 2: protection description bits 0-31 protection register address bits 32-39 n number of factory programmed regions (lower byte) bits 40-47 n number of factory programmed regions (upper byte) bits 48-55 2 n bytes in factory programmable region bits 56-63 n number of user programmable regions (lower byte) bits 64-71 n number of user programmable regions (upper byte) bits 72-79 2 n bytes in user programmable region 89h (p+14)h = 11eh 0000h 00h (p+15)h = 11fh 0000h 00h (p+16)h = 120h 0000h 00h (p+17)h = 121h 0000h 0 (p+18)h = 122h 0000h 0 (p+19)h = 123h 0000h 0 (p+1a)h = 124h 0010h 16 (p+1b)h = 125h 0000h 0 (p+1c)h = 126h 0004h 16 table 51. burst read information offset data description value (p+1d)h = 127h 0004h page-mode read capability bits 0-7 n? such that 2 n hex value represents the number of read-page bytes. see offset 0028h for device word width to determine page-mode data output width. 16 bytes (p+1e)h = 128h 0004h number of synchronous mode read configuration fields that follow. 4 (p+1f)h = 129h 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 0028h for word width to determine the burst data output width. 4 (p+20)h = 12ah 0002h synchronous mode read capability configuration 2 8 (p-21)h = 12bh (p+22)h = 12ch 0003h 0007h synchronous mode read ca pability configuration 3 16 synchronous mode read ca pability configuration 4 cont.
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl common flash interface 93/114 table 52. bank and erase block region information (1) 1. the variable p is a pointer which is defined at cfi offset 015h. flash memory (top) flash memory (bottom) description offset data offset data (p+23)h = 12dh 02h (p+23)h = 12dh 02h number of bank regions (2) within the device 2. bank regions. there are tw o bank regions, see tables 33 to 38 for the m58lr256gu/l and tables 39 to 44 for the M58LR128GU/l. table 53. bank and erase block region 1 information (1) (2) flash memory (top) flash memory (bottom) description offset data offset data (p+24)h = 12eh 0fh (p+24)h = 12eh 01h number of identical banks within bank region 1 (p+25)h = 12fh 00h (p+25)h = 12fh 00h (p+26)h = 130h 11h (p+26)h = 130h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+27)h = 131h 00h (p+27)h = 131h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+28)h = 132h 00h (p+28)h = 132h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+29)h = 133h 01h (p+29)h = 133h 02h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (3) (p+2a)h = 134h 0fh (4) (p+2a)h = 134h 03h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = num ber of bytes in erase block region 07h (5) (p+2b)h = 135h 00h (p+2b)h = 135h 00h (p+2c)h = 136h 00h (p+2c)h = 136h 80h (p+2d)h = 137h 02h (p+2d)h = 137h 00h
common flash interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 94/114 (p+2e)h = 138h 64h (p+2e)h = 138h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+2f)h = 139h 00h (p+2f)h = 139h 00h (p+30)h = 13ah 02h (p+30)h = 13ah 02h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+31)h = 13bh 03h (p+31)h = 13bh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+32)h = 13ch 0eh (4) bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = num ber of bytes in erase block region 06h (5) (p+33)h = 13dh 00h (p+34)h = 13eh 00h (p+35)h = 13fh 02h (p+36)h = 140h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+37)h = 141h 00h (p+38)h = 142h 02h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+39)h = 143h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved 1. the variable p is a pointer which is defined at cfi offset 015h. 2. although the device supports page read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. 3. bank regions. there are two bank regions, see tables 33 to 38 for the m58lr256gu/l and tables 39 to 44 for the M58LR128GU/l. 4. applies to m58lr256g devices. 5. applies to m58lr128g devices. table 53. bank and erase block region 1 information (1) (2) flash memory (top) flash memory (bottom) description offset data offset data
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl common flash interface 95/114 table 54. bank and erase block region 2 information (1) (2) flash memory (top) flash memory (bottom) description offset data offset data (p+32)h = 13ch 01h (p+3a)h = 144h 0fh number of identical banks within bank region 2 (p+33)h = 13dh 00h (p+3b)h = 145h 00h (p+34)h = 13eh 11h (p+3c)h = 146h 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+35)h = 13fh 00h (p+3d)h = 147h 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+36)h = 140h 00h (p+3e)h = 148h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+37)h = 141h 02h (p+3f)h = 149h 01h types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (3) (p+38)h = 142h 0eh (4) (p+40)h = 14ah 0fh (4) bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region 06h (5) 07h (5) (p+39)h = 143h 00h (p+41)h = 14bh 00h (p+3a)h = 144h 00h (p+42)h = 14ch 00h (p+3b)h = 145h 02h (p+43)h = 14dh 02h (p+3c)h = 146h 64h (p+44)h = 14eh 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+3d)h = 147h 00h (p+45)h = 14fh 00h (p+3e)h = 148h 02h (p+46)h = 150h 02h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved
common flash interface m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 96/114 (p+3f)h = 149h 03h (p+47)h = 151h 03h bank region 2 (erase block type 1):page mode and synchronous mode capabilities (defined in ta bl e 5 1 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+40)h = 14ah 03h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+41)h = 14bh 00h (p+42)h = 14ch 80h (p+43)h = 14dh 00h (p+44)h = 14eh 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+45)h = 14fh 00h (p+46)h = 150h 02h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+47)h = 151h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in ta bl e 5 1 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+48)h = 152h (p+48)h = 1 52h feature space definitions (p+49)h = 153h (p+43)h = 153h reserved 1. the variable p is a pointer which is defined at cfi offset 015h. 2. although the device supports page read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. 3. bank regions. there are tw o bank regions, see tables 33 to 38 for the m58lr256gu/l and tables 39 to 44 for the M58LR128GU/l. 4. applies to m58lr256g devices. 5. applies to m58lr128g devices. table 54. bank and erase block region 2 information (1) (2) (continued) flash memory (top) flash memory (bottom) description offset data offset data
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl flowcharts and pseudo codes 97/114 appendix c flowcharts and pseudo codes figure 22. program flowchart and pseudo code 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudo codes m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 98/114 figure 23. buffer program flowchart and pseudo code 1. n + 1 is the number of data being programmed. 2. next program data is an element belonging to buffer_progr am[].data; next program address is an element belonging to buffer_program[].address 3. routine for error check by reading sr3, sr4 and sr1. buffer program e8h command, start address ai08913b start write buffer data, start address yes x = n end no write n (1) , start address x = 0 write next buffer data, next program address x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) (2) read status register no sr7 = 1 yes buffer_program_command (start_address, n, buffer_program[] ) /* buffer_program [] is an array structure used to store the address and data to be programmed to the flash memory (the address must be within the segment start address and start address+n) */ { do {writetoflash ( start _address, 0xe8) ; status_register=readflash ( start _address); } while (status_register.sr7==0); writetoflash ( start _address, n); writetoflash (buffer_program[0].address, buffer_program[0].data); /*buffer_program[0].address is the start address*/ x = 0; while (x m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl flowcharts and pseudo codes 99/114 figure 24. program suspend & resume flowchart and pseudo code 1. the read status register command (write 70h) can be issu ed just before or just after the program resume command. write 70h ai10117b read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if program has completed */ } } write ffh program continues with bank in read status register mode read data write 70h (1)
flowcharts and pseudo codes m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 100/114 figure 25. block erase flowchart and pseudo code 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. write 20h (2) ai10976 start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl flowcharts and pseudo codes 101/114 figure 26. erase suspend & resume flowchart and pseudo code 1. the read status register command (write 70h) can be is sued just before or just after the erase resume command. write 70h ai10116b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues with bank in read status register mode write d0h read data from another block or program/protection register program or block lock/unlock/lock-down start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another block*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write 70h (1)
flowcharts and pseudo codes m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 102/114 figure 27. locking operations flowchart and pseudo code 1. any address within the bank can equally be used. write 01h, d0h or 2fh ai06176b read block lock states yes no locking change confirmed? start write 60h (1) locking_operation_command (address, lock_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl flowcharts and pseudo codes 103/114 figure 28. protection register program flowchart and pseudo code 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudo codes m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 104/114 figure 29. buffer enhanced factory program flowchart and pseudo code write 80h to address wa1 ai07302a start write d0h to address wa1 write ffffh to address = not wa1 read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx address wa1 increment count x = x + 1 initialize count x = 0 x = 32 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes sr4 = 1 no no no no setup phase program and verify phase exit phase buffer_enhanced_factory_program_command (start_address, dataflow[]) { writetoflash (start_address, 0x80) ; writetoflash (start_address, 0xd0) ; do { do { status_register = readflash (start_address); if (status_register.sr4==1) { /*error*/ if (status_register.sr3==1) error_handler ( ) ;/*v pp error */ if (status_register.sr1==1) error_handler ( ) ;/* locked block */ } while (status_register.sr7==1) x=0; /* initialize count */ do { writetoflash (start_address, dataflow[x]); x++; }while (x<32) do { status_register = readflash (start_address); }while (status_register.sr0==1) } while (not last data) writetoflash (another_block_address, ffffh) do { status_register = readflash (start_address) }while (status_register.sr7==0) full_status_register_check(); }
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface state tables 105/114 appendix d command interface state tables table 55. command interface states - modify table, next state (1) current ci state command input read array (2) ( ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)( 4) (20h) befp setup (80h) erase confirm p/e resume, block unlock confirm, befp confirm (3)(4) (d0h) buffer program, program/erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature, read cfi query (90h, 98h) ready ready program setup buffer program setup erase setup befp setup ready lock/cr setup ready (lock error) ready (unlock block) ready (lock error) otp setup otp busy busy program setup program busy busy program busy program suspend program busy suspend program suspend program busy program suspend buffer program setup buffer program load 1 (give word count load (n-1)); buffer load 1 if n=0 go to buffer program confirm. else (n not =0) go to buffer program load 2 (data load) buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) buffer program busy ready (error) busy buffer program busy buffer program suspend buffer program busy suspend buffer program suspend buffer program busy buffer program suspend erase setup ready (error) erase busy ready (error) busy erase busy erase suspend erase busy suspend erase suspend program in erase suspend buffer program setup in erase suspend erase suspend erase busy erase suspend program in erase suspend setup program busy in erase suspend busy program busy in erase suspend program suspend in erase suspend program busy in erase suspend suspend program suspend in erase suspend program busy in erase suspend program suspend in erase suspend
command interface state tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 106/114 buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)); if n=0 go to buffer program confirm. else (n not =0) go to buffer program load 2 buffer load 1 buffer program load 2 in erase suspend (data load) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this poi nt if any block address is different from the first address) confirm ready (error) buffer program busy in erase suspend ready (error) busy buffer program busy in erase suspend buffer program suspend in erase suspend buffer program busy in erase suspend suspend buffer program suspend in erase suspend buffer program busy in erase suspend buffer program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) buffer efp setup ready (error) befp busy ready (error) busy befp busy (6) 1. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller. 2. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active , both cycles are ignored. 5. the clear status register command clears the status regist er error bits except when t he p/e.c. is busy or suspended. 6. befp is allowed only when status register bit sr0 is set to ?0?. befp is busy if block address is first befp address. any other commands are treated as data. table 55. command interface states - modify table, next state (1) (continued) current ci state command input read array (2) ( ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)( 4) (20h) befp setup (80h) erase confirm p/e resume, block unlock confirm, befp confirm (3)(4) (d0h) buffer program, program/erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature, read cfi query (90h, 98h)
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface state tables 107/114 table 56. command interface states - modify table, next output state (1) (2) current ci state command input read array (3) (ffh) program setup (4) (5) (10/40h) buffer program (e8h) block erase, setup (4)(5) (20h) befp setup (80h) erase confirm, p/e resume, block unlock confirm, befp confirm (4)(5) (d0h) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h) program setup status register erase setup otp setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend lock/cr setup lock/cr setup in erase suspend
command interface state tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 108/114 otp busy array status register output unchanged status register output unchanged status register ready electronic signature/cfi program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank output state. 2. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller. 3. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 4. the two cycle command should be issued to the same bank address. 5. if the p/e.c. is active , both cycles are ignored. table 56. command interface states - modify table, next output state (1) (2) (continued) current ci state command input read array (3) (ffh) program setup (4) (5) (10/40h) buffer program (e8h) block erase, setup (4)(5) (20h) befp setup (80h) erase confirm, p/e resume, block unlock confirm, befp confirm (4)(5) (d0h) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h)
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface state tables 109/114 table 57. command interface states - lock table, next state (1) current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (4) wsm operation completed ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy n/a busy ready program setup program busy n/a busy program busy ready suspend program suspend n/a buffer program setup buffer program load 1 (give word count load (n-1)); n/a buffer load 1 buffer program load 2 (5) exit see note (5) n/a buffer load 2 buffer program confirm when count =0; else buffer prog ram load 2 (note: buffer program will fail at this point if any block address is different from the first address) n/a confirm ready (error) n/a busy buffer program busy ready suspend buffer program suspend n/a erase setup ready (error) n/a busy erase busy ready suspend lock/cr setup in erase suspend erase suspend n/a program in erase suspend setup program busy in erase suspend n/a busy program busy in erase suspend erase suspend suspend program suspend in erase suspend n/a buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)) buffer load 1 buffer program load 2 in erase suspend (6) exit see note (6) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) busy buffer program busy in erase suspend suspend buffer program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) n/a
command interface state tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 110/114 befp setup ready (error) n/a busy befp busy (7) exit befp busy (7) n/a 1. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller, wa0 = address in a block different from first befp address. 2. if the p/e.c. is active , both cycles are ignored. 3. befp exit when block address is different from first block address and data are ffffh. 4. illegal commands are those not defined in the command set. 5. if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 (data load). 6. if n=0 go to buffer program confirm in erase suspend. else (n 0) go to buffer program load 2 in erase suspend. 7. befp is allowed only when status register bit sr0 is set to ?0 ?. befp is busy if block address is first befp address. any other commands are treated as data. table 57. command interface states - lock table, next state (1) (continued) current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (4) wsm operation completed
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl command interface state tables 111/114 table 58. command interface states - lock table, next output state (1) (2) current ci state command input lock/cr setup (3) (60h) otp setup (3) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) wsm operation completed program setup status register output unchanged erase setup otp setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend lock/cr setup status register array status register lock/cr setup in erase suspend
command interface state tables m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl 112/114 otp busy status register output unchanged array output unchanged output unchanged ready program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank's output state. 2. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller, wa0 = address in a block different from first befp address. 3. if the p/e.c. is active , both cycles are ignored. 4. befp exit when block address is different from first block address and data are ffffh. 5. illegal commands are those not defined in the command set. table 58. command interface states - lock table, next output state (1) (2) (continued) current ci state command input lock/cr setup (3) (60h) otp setup (3) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) wsm operation completed
m58lr256gu, m58lr256gl, M58LR128GU, m58lr128gl revision history 113/114 revision history table 59. document revision history date version changes 05-jun-2006 1 initial release.
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